A typical digital signal processor (hereinafter, referred to as “DSP”) performs specialized signal processing architectures such as a Viterbi decoder, a FFT (Fast Fourier Transform) processor, and a LDPC (Low-density Parity-check Codes) decoder. Generally, the DSP uses an embedded memory to perform such architectures. In this case, as the embedded memory, a logic processor, i.e., a SRAM (static random-access memory) which can be implemented by a general process is mainly used.
Meanwhile, as for the embedded memory used in the DSP, read and write access patterns are determined by an architecture. Therefore, as for the embedded memory used in the DSP, exact timings for reading and writing can be predicted by analysis of architecture. A memory access pattern of a DSP module will be described as follows with reference to FIG. 1 and FIG. 2.
FIG. 1 is a diagram illustrating an example of a memory access pattern of a Viterbi decoder. And FIG. 2 is a diagram illustrating an example of a memory access pattern of a FFT processor.
A memory access pattern of a Viterbi decoder as a DSP has a certain rule as illustrated in FIG. 1. Further, the Viterbi decoder has a certain cycle to a last read operation after a write operation. That is, in the Viterbi decoder, a memory access pattern is repeated by 384 cycles, which is a period of time required for completing data input/output. As such, the Viterbi decoder has a certain memory access pattern.
A FFT processor illustrated in FIG. 2 performs memory read and write operations regularly depending on a butterfly architecture. In the FFT processor, the longest period of time during a cycle to a last read operation after a write operation is smaller than the number of cycles per stage. That is, it corresponds to 64 cycles in FIG. 2. Further, a LDPC decoder also has a certain cycle in which a memory access pattern is determined by an architecture.
As such, a DSP operated on the basis of a certain rule such as a certain access pattern and a certain cycle does not need a refresh operation if the DSP uses a SRAM. However, a memory cell of the SRAM is several times greater in size than a memory cell of a DRAM. On the other hand, if a DRAM is used, electric charges stored in a memory cell may continuously leak, a DSP additionally needs a refresh operation. However, the refresh operation in the DRAM consumes a lot of electricity. Therefore, the present disclosure suggests an algorithm of a DSP in which a DRAM is used but a refresh operation may be omitted.
In this regard, Korean Patent Application Publication No. 10-2006-0097565 (entitled “Dynamic random access memories and method for testing performance of the same”) discloses a technology that enables screening of a so-called variable retention time (VRT) failure, i.e., a retention failure occurring in a DRAM due to fluctuation of data retention time like a random telegraph noise.
Further, Korean Patent No. 10-0505832 (entitled “Dynamic DRAM refresh rate adjustment based on cell leakage monitoring”) discloses a technology that enables designing a DRAM leakage monitor such that it is pre-charged when a chip enters a self-refresh cycle, measuring a leakage monitor cell, and converting information on a remaining charge level in the cell into digital output signals that will determine a refresh rate for the following refresh cycle.